1. Field of Invention
The present invention relates to a power supply, and more particularly, the present invention relates to a power supply with open-loop protection.
2. Description of Related Art
In general, power supplies have been widely used to provide stable voltage and current. Based on the restriction of the safety provision, power supply must provide an Open-loop protection and a brown-out protection for preventing the power supply itself and the circuits of the load terminal from the influence. FIG. 1 shows a circuit diagram of a traditional power supply with the open-loop protection. The traditional power supply comprises a transformer T1, a driving circuit 14, a signal generation circuit 10, an oscillator 12, a power switch Q1, a feedback detection circuit 16 and a delay circuit 18.
Referring to FIG. 1, the transformer T1 has a primary winding NP and a secondary winding NS for the energy storage and the power conversion. The transformer T1 is coupled to an input voltage VIN of the power supply. The energy stored in primary winding NP of the transformer T1 is converted to the secondary winding NS while the transformer T1 is switched by the power switch Q1. The energy converted to the secondary winding NS is regulated by an output rectifier DO and an output capacitor CO to generate an output voltage VO. The current sense device RS is coupled to the power switch Q1 in series. The current sense device RS generates a current signal VCS in response to a primary switching current IP from the transformer T1. Otherwise, a feedback signal VFB is provided from the output voltage VO of the power supply to the driving circuit 14 and the feedback detection circuit 16 through a feedback manner.
The driving circuit 14 consists of a logic circuit 144, a power limit comparator 146 and a pulse width modulation (PWM) comparator 148. The driving circuit 14 generates a reset signal CLR to disable the switching signal VPWM in response to the current signal VCS, a power limit signal VLMT and the feedback signal VFB. An input terminal of the power limit comparator 146 and an input terminal of the PWM comparator 148 both are coupled to the current sense device RS for receiving the current signal VCS. Another input terminal of the power limit comparator 146 receives the power limit signal VLMT, and another input terminal of the PWM comparator 148 receives the feedback signal VFB.
An output terminal of the power comparator 146 generates an over current signal OC that is in a low level when the current signal VCS is higher than the power limit signal VLMT. Furthermore, An output terminal of the PWM comparator 148 generates a feedback control signal CNTR that is in the low level when the current signal VCS is higher than the feedback signal VFB. Two input terminals of the logic circuit 144 are coupled to the output terminals of the power comparator 146 and the PWM comparator 148 respectively. Therefore, an output terminal of the logic circuit 144 generates the reset signal CLR that is in the low level for disabling the switching signal VPWM in response to the over current signal OC and/or the feedback control signal CNTR. In other words, the driving circuit 14 determines the logic level of the reset signal CLR in response to the logic level of the feedback control signal CNTR or the over current signal OC.
The signal generation circuit 10 comprises a logic circuit 101, a flip-flop 103 and a logic circuit 105. The logic circuit 101 is an inverter. An input terminal of the logic circuit 101 is coupled to the oscillator 12 for receiving a pulse signal PLS outputted from the oscillator 12. An output terminal of the logic circuit 101 is coupled to a clock input terminal CK of the flip-flop 103 for driving the flip-flop 103. An input terminal D of the flip-flop 103 is coupled to an output terminal of the delay circuit 18. An output terminal Q of the flip-flop 103 is coupled to an input terminal of the logic circuit 105. Another input terminal of the logic circuit 105 receives the pulse signal PLS via the logic circuit 101. An output terminal of the logic circuit 105 generates the switching signal VPWM. The logic circuit 105 is an AND gate. A reset input terminal R of the flip-flop 103 is coupled to the output terminal of the driving circuit 14 for receiving the reset signal CLR.
The signal generation circuit 10 is coupled to the output terminals of the oscillator 12 and the driving circuit 14. The signal generation circuit 10 generates the switching signal VPWM in response to the pulse signal PLS outputted from the oscillator 12. The switching signal VPWM controls the switch of the power switch Q1. The signal generation circuit 10 periodically adjusts the pulse width of the switching signal VPWM in response to the reset signal CLR outputted from the driving circuit 14 for regulating the output voltage VO of the power supply in stable and limiting the output power.
Referring to FIG. 1, two input terminals of the feedback detection circuit 16 receives the feedback signal VFB and a threshold signal VTH respectively for generating a pull-high signal SPH. The feedback signal VFB is lower than the threshold signal VTH when the power supply is in a normal operation condition. In the meanwhile, an output terminal of the feedback detection circuit 16 generates the pull-high signal SPH that is in the low level. The delay circuit 18 doesn't count and outputs a disabling signal SOFF that is in a high level to the signal generation circuit 10 when the delay circuit 18 receives the pull-high signal SPH that is in the low level. The signal generation circuit 10 doesn't latch the switching signal VPWM when the signal generation circuit 10 receives the disabling signal SOFF that is in the high level.
In contrast, the level of the feedback signal VFB will be pulled to high to reach a supply voltage VCC via a pull-high resister RPH when an open-loop condition is occurred at the output terminal of the power supply. The output terminal of the feedback detection circuit 16 generates the pull-high signal SPH that is in the high level when the level of the feedback signal VFB is pulled to high to be higher than the threshold signal VTH. The delay circuit 18 starts to count in response to the pull-high signal SPH that is in the high level, and generates the disabling signal SOFF that is in the low level after a delay time. The signal generation circuit 10 will latch the switching signal VPWM in response to the disabling signal SOFF that is in the low level. Therefore, when the level of the feedback signal VFB is pulled to high, the feedback detection circuit 16 and the delay circuit 18 controls the signal generation circuit 10 to latch the switching signal VPWM for the open-loop protection.
Besides, the power supply has a brown-out protection circuit (not shown in FIG. 1). The brown-out protection circuit counts a delay time when the input voltage VIN of the power supply is in a brown-out condition. Then, the brown-out protection circuit latches the switching signal VPWM for the brown-out protection after the brown-out protection circuit counts the delay time completely. The delay time required for the brown-out protection is longer than the delay time required for the open-loop protection. Actually, if the occurring time of brown-out condition is shorter than the delay time of the brown-out protection, the brown-out protection is not needed to be executed. It is to say, latching the switching signal VPWM is not necessary. However, once the input voltage VIN is in the brown-out condition the level of the feedback signal VFB is pulled to high to reach the supply voltage VCC via the pull-high resister RPH. Further, the delay time of the open-loop protection is shorter than the delay time of the brown-out protection. Accordingly, the brown-out protection is not needed to be executed when the brown-out condition is occurred and the occurring time of the brown-out condition is shorter than the delay time of the brown-out protection, but the open-loop protection is executed firstly to latch the switching signal VPWM before the brown-out protection is executed. Therefore, it causes a miscarriage of latching the switching signal VPWM. For the power supply design, it has become a major concern how the power supply distinguishes accurately between the open-loop protection and the brown-out protection when the delay time of the brown-out protection can't be shortened.